1. Field of the Invention
The present disclosure generally relates to the fabrication of semiconductor devices, and, more particularly, to methods for forming transistor devices with different source/drain contact liners and the resulting devices.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device 100 that is formed above a semiconductor substrate 105 at an intermediate point during fabrication. In this example, the FinFET device 100 includes three illustrative fins 110, an isolation material 130, a gate structure 115, sidewall spacers 120 and a gate cap layer 125. The fins 110 have a three-dimensional configuration: a height, a width, and an axial length. The portions of the fins 110 covered by the gate structure 115 are the channel regions of the FinFET device 100, while the portions of the fins 110 positioned laterally outside of the spacers 120 are part of the source/drain regions of the device 100. Although not depicted, the portions of the fins 110 in the source/drain regions may have additional epi semiconductor material formed thereon in either a merged or unmerged condition.
In an integrated circuit device, there are different performance requirements for different functional blocks or regions of the device, i.e., there may be different performance specifications for devices formed in a logic region as compared to devices formed for input/output circuitry or in a memory region. It is useful to provide different materials for the source/drain contacts for the NMOS and PMOS transistors. Generally, different materials are optimal for the different type transistor devices. However, providing different materials in the different regions significantly complicates the process flow. For example, it is common to selectively form a first liner for a first type of device (i.e., PMOS or NMOS) only in a first contact opening for the first device, form a second liner for the second type of device in the first and second contact openings of both devices, and fill the remainder of the first and second contact openings with a conductive material. Because the first contact opening for the first type of device includes two liners, while the second contact opening only has a single liner (i.e., the second liner), the aspect ratio of the first contact opening is reduced relative to the aspect ratio of the second contact opening. Accordingly, there is a reduced amount of the conductive material in the first contact opening as compared to the second contact opening and a corresponding increased contact resistance for the first contact formed in the first contact opening as compared to the second contact formed in the second contact opening.
The present disclosure is directed to various methods and resulting devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.